1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of integrated circuits having data retention latches used to retain the state of the integrated circuit in a standby mode, during which the integrated circuit does not perform processing operations.
2. Description of the Prior Art
It is known to provide data retention latches (sometimes referred to as balloon latches) within integrated circuits for the purpose of retaining state data in a low power standby mode of operation. These data retention latches can be formed to have electrical characteristics well suited to their low power standby mode type of operation, e.g. they can have a high threshold voltage resulting in low leakage current losses. Such low power characteristics are normally not suitable for use in the operational circuits which must switch at high speed during data processing. However, the data retention latches need not operate at high speed and so can be engineered with low power consumption in mind. When entering the standby mode, the state data is typically transferred from the operational latch into the data retention latch and then the operational latch is powered down. On exiting the standby mode, the stored data value held within the data retention latch is forced back from the data retention latch into the operational latch and processing operations are recommenced. This provides advantageously rapid entry and exit from standby mode without data loss.
A problem associated with the use of data retention latches in this way is the large number of data retention latches which typically need to be provided on an integrated circuit to hold sufficient of its state that processing operations can be stopped and restarted without data loss. The circuit area consumed by such a large number of data retention latches is a disadvantageous overhead.
It has been proposed that in order to achieve better performance, in terms of speed and/or energy consumption, operational latches within an integrated circuit should be associated with delayed latches serving to capture the same signal value as the operational latch but at a slightly later time. The two captured values can then be compared and if the delayed captured value differs from the earlier captured value, then corrective action may be taken. Such an arrangement allows the circuit to be operated closer to the limiting levels of speed and/or voltage etc. Such an arrangement will typically control operational parameters such that a finite error rate is maintained in a recognition that the penalty associated with recovering from such errors is more than outweighed by the advantages achieved in running closer to the operational limits of the integrated circuit.